Metal Oxide Semiconductor (MOS) type transistors are a fundamental building block within integrated circuits. Consequently, there is a persistent push to make such devices smaller, faster, etc. An MOS transistor, includes a body region of a first semiconductor type (e.g. a P-type region). The body region has two spaced regions (source and drain) of the opposite semiconductor type (e.g. N-type). Typically, the source and drain regions have lightly doped extension regions of the same semiconductor type (N-type, in our example) although the doping concentration is lower. The region of the body between the source and drain is referred to as the “channel.” The extension regions help overcome short channel transistor effects as device dimensions continue to shrink. A doped polysilicon gate overlies a thin gate oxide. The gate and oxide overly the channel region in the body, between the source and drain.
The silicon-on-insulator (SOI) type MOS structure was developed to improve performance, for example by reducing junction capacitances. This technology involves forming the MOS transistor on an insulating region. The SOI transistor has components similar to the MOS transistor device formed on a bulk semiconductor substrate as described above, however, the body overlies an insulating layer, such as silicon dioxide (SiO2). The insulating layer, in turn, overlies a bulk semiconductor material. Conventional SOI types of structures have evolved and basically comprise a substrate, such as a silicon-containing substrate, an insulating layer thereon, commonly referred to as a buried oxide layer, and a monocrystalline silicon layer on the insulating layer which constitutes the “body” of the transistor.
An SOI based transistor structure provides several performance advantages over traditional bulk transistor devices. For example, each device in an SOI structure is completely isolated from all other devices (as opposed to sharing a common substrate body). Consequently, the SOI provides better individual device isolation, which prevents circuit latch-up conditions. Also, in most SOI devices, at least a portion of each source or drain region abuts the underlying insulating layer. As a result, the cross sectional area of the source/drain interfaces to the semiconductor body are reduced, and this reduces the junction capacitances. When an electrical signal changes on either or both source/drain regions, there is no capacitive coupling to the substrate. Certain electrical elements of the circuit can be positioned closer together, thereby reducing the die size. SOI structures offer the advantages of latch-up immunity, reduced junction leakage currents and reduced short channel effects, thereby translating to increased transistor speed.
In SOI devices, the body floats in that there is no direct electrical connection thereto. In some cases, this can be disadvantageous. “Floating body effects” are a class of hysteresis effects produced because the voltage of the semiconductor body is allowed to float relative to ground. Examples of floating body effects include the “kink” effect and the parasitic lateral bipolar effect. The “kink” effect originates from impact ionization. When the SOI transistor is operated at a relatively high drain-to-source voltage, channel electrons having sufficient kinetic energy cause an ionizing collision with the lattice, resulting in carrier multiplication near the drain end of the channel. The generated holes build up in the body of the device, thereby raising the body potential. The increased body potential reduces the threshold voltage of the transistor, thus increasing the transistor current, which results in a “kink” in the transistor current/voltage curves. If impact ionization generates a large number of holes, the body bias may be raised to a sufficient voltage so that the source/body p-n junction becomes forward biased. When this junction becomes forward biased, minority carriers are emitted into the body, which causes a parasitic lateral npn bipolar transistor to turn on. This parasitic lateral bipolar transistor effect leads to a loss of gate control of the transistor current and is therefore highly undesirable.
The flow of current between the gate and the body is a relevant parameter having an impact on the above-noted floating body effects. To assess such effects, it is useful to measure the gate-body current of an SOI transistor. However, existing techniques involve making a body tie or connection to the body of the actual device (that otherwise would be floating) and measuring current flow between the gate and the tied body. Characterization or measurement of this component in this manner is difficult, since tied-body structures used to extract the measure of the gate-body current introduce a large error due to the body tie connection to the device. Essentially, the extrinsic gate-body current in a device that has a tie or contact to the body for the measurement overwhelms the intrinsic gate-body current produced solely by the device operation without the tie, due to the topology/behavior of the body tie. Often, the extrinsic gate-body current due to the body tie is 10 to 100 times larger than the intrinsic gate-body current.
In developing and scaling MOS technologies, it is also useful to know the physical gate length. However, there currently is no convenient technique for directly measuring the physical gate length of an MOS transistor, in SOI or bulk technologies.
Hence, there is a need for a test structure and a testing technique, which enable the desirable testing of gate-body current and physical gate length. To provide the needed test structure, there is an attendant need for a technique to construct the test structure, so as to enable accurate measured representation of the parameters relevant to the actual MOS devices.